TableGen
Is a convinient language used within the LLVM project to generate and maintain a variety of file types. It is especially useful when manual maintenance would be very difficult.
One example of its use is to define all of the instructions that can be used on a particular architecture. This information is captured in TableGen and then, the single source file can be used to produce many things such as C++ code, documentation, command line options etc.
TableGen has been in existence since
before
the first official release of LLVM, over 20 years ago. Currently, in the LLVM project repository, there are over a thousand TableGen source files totalling over 500,000 lines of code, making it the 5th most popular language in the repository.
Language
files
blank
comment
code
C++
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958542
1870101
5544445
C/C++ Header
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316806
499845
1486165
C
10535
259900
1603594
1011269
Assembly
10694
478035
1222315
820236
TableGen
1312
94112
83616
580289
(Counted from
this commit,
rest of table omitted)
With projects such as MLIR
embracing TableGen,
it is only going to grow. So if you are contributing to LLVM, you will encounter
it at some point.
Which might be a problem as TableGen only exists within LLVM. Unlike a language
such as C++, TableGen does not have a large array of resources.
So, as well as joining a new project, you also need to learn a new
Domain Specific Language (DSL). You did not come to LLVM to learn a DSL, you
probably came here to write a compiler.
I cannot say when this problem might be solved, but the situation is not as
bleak as it appears. There have been big improvements in TableGen tools
recently, which means you can put more of your energy into the goals that
brought you to LLVM in the first place.
A Brief Introduction to TableGen
Imagine you wanted to represent the registers of an architecture. I am going to
use Arm’s AArch64 in particular here.
You could describe them in TableGen as:
$ cat register.td
class Register
int size = _size;
string alias = _alias;
}
// 64 bit general purpose registers are X
def X0: Register<8> {}
// Some have special alternate names.
def X29: Register<8, "frame pointer"> {}
// Some registers omitted…
By default, the TableGen compiler llvm-tblgen creates “records” – which are
shown below.
$ ./bin/llvm-tblgen register.td
————- Classes —————–
class Register
int size = Register:_size;
string alias = Register:_alias;
}
————- Defs —————–
def X0 { // Register
int size = 8;
string alias = “”;
}
def X29 { // Register
int size = 8;
string alias = “frame pointer”;
}
This is the intermediate representation (IR) of the TableGen compiler, similar
to LLVM’s “LLVM IR”.
When using LLVM you would select a “target” which is the processor architecture
you want to generate instructions for.