Innovative Approaches to Lithography for Semiconductor Chip Technology
The semiconductor industry is constantly striving to create smaller and more efficient electronic components, a challenge that is especially prominent in the realm of lithography. Lithography is the process used to produce intricate patterns on semiconductor wafers, crucial for the development of advanced chips.
Enhancing Resolution and Manufacturability
Central to lithography is the use of photomasks, or masks, to generate patterns on wafers. The industry is continuously seeking methods to enhance resolution and manufacturability for both masks and wafers to produce faster chips with higher yields of operational chips.
Computational Lithography Advancements
Computational lithography techniques, like optical proximity correction (OPC), have made significant progress in improving resolution and pattern fidelity. These techniques modify individual mask patterns to enhance both mask and wafer printing processes.
The Promise of Inverse Lithography Technology (ILT)
Inverse lithography technology (ILT) presents a mathematically rigorous approach to determine mask shapes that yield desired on-wafer results. Curvilinear ILT mask shapes have shown promise in delivering optimal wafer results in several studies conducted over the past decade.
Breakthroughs in ILT Implementation
Until recently, the use of ILT in practical applications was hindered by runtime constraints, limiting its applicability to critical chip hotspots. In 2019, a novel system incorporating GPU acceleration technology facilitated full-chip ILT solutions, making it a viable option for production.
Challenges in Implementing ILT with VSB Mask Writers
However, the adoption of multi-beam mask writing posed challenges for variable shaped beam (VSB) mask writers, which predominantly operate based on rectilinear shapes. While VSB writers offer quick generation of large rectangular shapes, the complexity of intricate mask patterns can result in extended writing times due to the need for numerous small rectangles.
The Birth of Mask Wafer Co-optimization (MWCO)
The pioneering team at D2S, Inc., introduced the concept of mask wafer co-optimization (MWCO) to address these challenges. By recognizing the mask writer and wafer scanner as low-pass filters and employing overlapping shots guided by mask/wafer simulation, MWCO enables the creation of curvilinear shapes with reduced shot counts.
To learn more about this groundbreaking work, refer to the Journal of Micro/Nanopatterning, Materials, and Metrology.